Program

Rubin, MI400 and Crescent Island on compute, Vera, Arm AGI and Diamond Rapids on CPUs, HBM4 base-die logic and LPDDR5X-PIM on memory, the packaging and Chips Act 2.0 signals from SEMICON Europa, and the three vendor claims the analyst does not believe.

Connection queues, transformer lead times, and what a 200 MW commitment looks like from the grid’s side.

The financing layer under the accelerator orders: vendor financing, neocloud debt, lease structures, and where a slowdown would show first. Numbers only, no attribution.

The AICA thesis in five minutes and the house rules: architects present their own chips, no vendor stage, named skeptics, Chatham House rooms marked, awards at the close of the day.

Bytes: decode-phase inference sits on the memory-bandwidth roofline, the KV cache is a first-order budget line, and the 2026 silicon roadmap was redesigned around it. Joules: the AI energy wall from picojoules per bit to megawatts per hall, and what optimal server design and operation looks like when energy is the scarce input. Trust: verifying systems whose components are sampled, from formal guards on agents to reproducible failure diagnosis. The chair closes with the three questions the rest of the program must answer.

Two European accelerator teams disclose die floor plan, memory subsystem, numerics, interconnect, measured performance per watt on stated workloads, and the trade they regret. No roadmap slides. Questions limited to the architecture on screen.

HBM4’s doubled interface width and logic-process base die, bandwidth and capacity per watt of each tier, 3D DRAM for generative inference, and where high-bandwidth flash fits. Exercises included.

Bytes per token for dense and MoE models at production batch sizes, HBM bandwidth against compute at each accelerator generation, CXL 3.0 pooling latency against HBM and DRAM, KV-cache tiering, and processing-in-memory for the GEMV operations of decode.

Show the incident: model-FLOP utilisation achieved against theoretical, checkpoint cadence against measured mean time between failures at thousands of accelerators, the network failure that cost a week, the silent data corruption that cost more.

One fused-MoE kernel task on two targets. Teams receive the task, harness and device rooflines at 11:00, submit at 12:25, and see a live leaderboard of measured throughput with a correctness gate.

Authors of five 2026 papers from ISCA, MICRO, HPCA and ASPLOS: what the paper showed, what it measured, what the industry did with it. Topics: LLM systems, processing-in-memory, chiplets and wafer-scale, sustainability.

Commit to this accelerator generation now or wait for the next, given lead times, depreciation and the inference-share shift. One note-taker, no attribution.

One generation of in-house accelerator against the merchant part it displaced: the workload it was built for, memory choices, interconnect, the software cost that dwarfed the silicon, and the make-or-buy arithmetic (NRE, mask sets, volume needed to beat merchant TCO).

Student Research Competition posters in the foyer through lunch.

Where margin pools form as the stack commoditises around them (foundry, packaging, memory, accelerator, interconnect, cloud, model) and which layer is most likely to be squeezed in 2027. Q&A limited to questions with numbers in them.

Accelerator unit volumes and ASPs, HBM supply against demand, CoWoS capacity, hyperscaler capex guidance against free cash flow, the depreciation schedules under dispute, and the leading indicators each analyst watches for a turn. Each names the point at which they would change their view.

The proposer defends with returns per marginal training FLOP, test-time compute scaling curves and the post-training share of budget. The opponent answers with data quality, architecture change and the base-model dependency of inference-time methods. The result is published.

A CXL controller under real inference load, a rowhammer mitigation at fleet scale, and kernel optimisation on a shipping accelerator. Three minutes of questions each, one shared discussion.

Standards and profiles, RISC-V hosts interoperating with merchant GPUs, vector and matrix extensions for inference, and where European RISC-V accelerator programs stand. Hands-on: run an inference kernel on a RISC-V vector target.

Scale-up domain size against the largest trainable shard, all-reduce cost against bisection bandwidth, high-radix switching against Ethernet scale-out and proprietary fabrics on bandwidth per port, picojoules per bit, failure blast radius and openness, then co-packaged optics with link budgets and laser reliability.

Prefix-cache hit rates and what they saved, model routing across a cost-quality frontier, speculative decoding acceptance rates in production, and the batch-size-versus-latency curve that sets price. Every talk ends with cost per million tokens before and after.

Teams drive an LLM agent to generate RTL for a small accelerator block, push it through simulation and formal equivalence, and score on the fraction of generated designs that pass formal, not synthesis.

Authors of five 2026 papers from MLSys, OSDI, SOSP and NeurIPS on efficient training and serving, compilers and runtimes, and compound AI systems. What it measured and what shipped.

The afternoon’s Analyst Review analysts teach their method: which series lead (HBM contract pricing, CoWoS bookings, hyperscaler capex guidance, DRAM spot), how to build a die-cost model, and how they were wrong last cycle. Participants leave with the spreadsheet.

The device engineer on what a multiply-accumulate costs at the node in energy and area, the circuit designer on block-scaled datapaths and accumulation precision, the model architect on where FP4 weights and activations break and what calibration recovers. Fifteen minutes each, and each must reference the other two.

Every panellist states one number that would change their mind.

PhD students present the direction of work in progress, then stand by their posters in the foyer.

Silicon on a board, a kernel on a device, an agent harness under load. Working systems only. The Best Demo jury scores here.

Evening mixer in the foyer. The Chair’s dinner (14 seats, closed) runs alongside, with a guest list drawn from Day 1 speakers plus two Research Preview presenters, hosted by the General Chair.